The present patent application relates to a semiconductor memory cell and a method for fabricating it. The semiconductor memory cell contains a selection transistor and a trench capacitor formed in a trench.
Memory devices, such as dynamic random access memories (DRAMs), for example, contain a cell array and an addressing periphery, individual memory cells being disposed in the cell array.
A DRAM chip contains a matrix of memory cells that are disposed in the form of rows and columns and are addressed by word lines and bit lines. Data are read from the memory cells or data are written to the memory cells by the activation of suitable word lines and bit lines.
A DRAM memory cell usually contains a transistor connected to a capacitor. The transistor contains, inter alia, two diffusion regions separated from one another by a channel controlled by a gate. One diffusion region is referred to as the drain region and the other diffusion region is referred to as the source region.
One of the diffusion regions is connected to a bit line, the other diffusion region is connected to the capacitor and the gate is connected to a word line. By applying suitable voltages to the gate, the transistor is controlled in such a way that a current flow between the diffusion regions through the channel is switched on and off.
The integration density is continuously increased by the advancing miniaturization of memory devices. The continuous increase in the integration density results in that the area available per memory cell decreases further and further. If the selection transistor is formed as a planar transistor, for example, then the lateral distance between the selection transistor and the trench capacitor consequently decreases further and further. That leads to a reduction of the blocking capability of the selection transistor, which blocks more poorly with decreasing channel length on account of the short-channel effect. The increased leakage currents discharge the trench capacitor prematurely, as a result of which the information stored in the trench capacitor and the memory cell is lost.
The short-channel effects are intensified by the outdiffusion of a buried strap. The buried strap is usually disposed in the trench capacitor above the conductive trench filling and serves for electrically connecting the conductive trench filling to a doping region of the transistor. In this case, an outdiffusion of dopant from the buried strap into the substrate and the adjoining doping region of the selection transistor is usually carried out, thereby forming the electrical contact. What is disadvantageous about a conventional buried strap is that it intensifies the short-channel effects that occur.
A further problem known from the prior art is that the doping region of the selection transistor is usually to be formed in monocrystalline silicon in order to avoid leakage currents through the selection transistor. Since the buried strap is usually formed from polycrystalline silicon which adjoins the monocrystalline silicon of the doping region of the selection transistor, at elevated temperatures crystal dislocations are formed in the monocrystalline silicon proceeding from the interface between polysilicon and monocrystalline silicon, and can lead to leakage currents through the selection transistor.
What is disadvantageous about an epitaxially grown buried strap is that crystal dislocations are formed at the transition between the silicon grown epitaxially in monocrystalline form and silicon grown in polycrystalline form. This defect formation leads to increased leakage currents in the selection transistor. During the further fabrication process of the DRAM, the dislocations move and can short-circuit the selection transistor.
Fabrication methods for DRAM memory cells having a trench capacitor and selection transistor are specified for example in U.S. Pat. Nos. 5,360,758, 5,670,805 and 5,827,765 and the reference by U. Gruening et al. title xe2x80x9cA Novel Trench DRAM Cell with a Vertical Access Transistor and Buried Strap for 4 Gb/16 Gbxe2x80x9d, IEDM, 1999.
It is accordingly an object of the invention to provide a semiconductor memory cell and a method for fabricating the memory cell that overcome the above-mentioned disadvantages of the prior art devices and methods of this general type, which enables an improved doping profile of the buried strap and avoidance of crystal defects in the selection transistor. With the foregoing and other objects in view there is provided, in accordance with the invention, a method for fabricating a semiconductor memory having a trench capacitor and a selection transistor. The method includes providing a substrate having a substrate surface with a trench formed therein, forming an insulation collar in an upper region of the trench and on a sidewall of the trench, depositing a dielectric layer functioning as a capacitor dielectric on the insulation collar, providing a conductive trench filling in the trench, sinking the conductive trench filling into the trench to a first sinking depth, removing the dielectric layer from the insulation collar in a region above the first sinking depth, sinking the conductive trench filling into the trench to a second sinking depth, uncovering the substrate at the sidewall of the trench above the conductive trench filling resulting in an uncovered sidewall, growing an epitaxial layer on the uncovered sidewall of the trench, forming an intermediate layer on the epitaxial layer, introducing a dopant into the epitaxial layer, and completing the trench capacitor and the selection transistor.
One advantage of the epitaxially grown layer is that the dopant outdiffused from the buried strap has a shorter diffusion length in the epitaxially grown layer than in the adjoining bulk silicon in which the selection transistor is formed. This has the result that the dopant outdiffused from the buried strap does not diffuse right into the channel of the selection transistor, thereby preventing intensification of the short-channel effect in the selection transistor. The first intermediate layer has the advantage that crystal dislocations formed in the buried strap do not grow into the monocrystalline substrate in which the selection transistor is disposed. Crystal defects are thereby avoided at the doping region of the transistor, whereby it is possible to achieve an improved transistor with small leakage currents.
It is preferably provided that the epitaxially grown layer is disposed on the sidewall of the trench above the insulation collar in the direction of the substrate surface. This improves the dopant profile of the outdiffusion above the insulation collar.
Usually, a capacitor dielectric is disposed in the trench between the conductive trench filling and the substrate.
A further refinement of the invention provides for the selectively epitaxially grown layer (SEG: selective epitaxial growth) to have a facet having an angle of approximately 45 degrees relative to the substrate surface. The facet has the advantage that the electrical resistance between the doping region of the transistor and the conductive trench filling is reduced on account of the facet geometry. The facet is, for example, a natural crystal orientation of silicon.
A further refinement provides for the facet to be situated at the lower end of the epitaxially grown layer above the insulation collar. In particular, it is provided that a barrier layer is introduced in an annular gap formed by the facet and the upper edge of the insulation collar, which barrier layer prevents a diffusion of dopants to the sidewall of the trench. Since the thickness of the epitaxially grown layer decreases towards the upper and lower edges, it is advantageous to fill the annular gap which is produced at the lower edge and is formed by the facet and the upper edge of the insulation collar with a diffusion-blocking material before the trench filling is introduced, which is generally composed of polysilicon with dopants added to it, which can diffuse into the substrate beside the sidewall of the trench.
It is preferably provided that a dopant is introduced in the epitaxially grown layer and the adjoining substrate in order to form a conductive electrical connection to the buried strap. The introduced dopant has the advantage that a low-resistance electrical connection is made possible between the conductive trench filling and the doping region of the selection transistor. The introduced dopant is usually referred to as buried strap outdiffusion, since it is usually diffused out of the buried strap into the substrate.
It is preferably provided that the trench isolation has an insulation layer disposed on the buried strap and on the facet. The insulation layer disposed on the buried strap and on the facet has the advantage that, in the case of a planar selection transistor, a passing word line insulated from the trench capacitor can be disposed on the trench isolation. In the case of a memory cell with a vertical selection transistor, an active word line for driving the cell transistor runs above the trench.
A further refinement of the invention provides for the insulation collar to contain two layers that can be etched selectively with respect to one another.
With regard to the method, the object according to the invention is achieved by a method for fabricating a semiconductor memory having a trench capacitor and a selection transistor. A substrate is provided which has a substrate surface and in which a trench having an upper region is disposed. An insulation collar is disposed in the upper region on the sidewall of the trench. A conductive trench filling is disposed in the trench, and the conductive trench filling is subsequently sunk into the trench. The substrate is uncovered at the sidewall of the trench above the conductive trench filling. An epitaxial layer is grown on the uncovered sidewall of the trench. A first intermediate layer is formed on the epitaxially grown layer. A dopant is introduced into the epitaxially grown layer, and the trench capacitor and the selection transistor are finished.
The method according to the invention contains steps for forming the first intermediate layer and for forming the epitaxially grown layer which have the advantages described in connection with the way in which the object is achieved in respect of the subject-matter.
It is preferably provided that the substrate is uncovered at the sidewall of the trench by removing an upper part of the insulation collar. The epitaxial layer can thus be applied above the insulation collar in the direction of the substrate surface.
It is preferably provided that after the provision of the substrate, a dielectric layer of a capacitor dielectric is deposited onto the insulation collar before the conductive trench filling is formed, and in that the conductive trench filling is first sunk into the trench as far as a first sinking depth, the dielectric layer is subsequently removed from the insulation collar above the first sinking depth and the conductive trench filling is then sunk into the trench as far as a second sinking depth before the substrate is uncovered above the conductive trench filling. In this case, the depth to which the insulation collar is removed is set with the aid of the capacitor dielectric.
As an alternative to this, it is provided that a substrate is provided which already has a capacitor dielectric in a lower region of the trench, the capacitor dielectric having been introduced before the formation of the insulation collar, and in that the dielectric layer is deposited on the insulation collar only after the formation of the insulation collar. In this case; after the formation of the insulation collar, a further dielectric layer is applied thereto in order to set the depth to which the insulation collar is removed.
A first variant of the last-mentioned type of embodiment provides that the conductive trench filling is first sunk into the trench as far as a first sinking depth, the dielectric layer is subsequently removed from the insulation collar above the first sinking depth and the conductive trench filling is then sunk into the trench as far as a second sinking depth before the substrate is uncovered above the conductive trench filling. In this case, the dielectric layerxe2x80x94like the capacitor dielectric otherwisexe2x80x94is removed after a first etching-back of the trench filling, thereby defining the depth to which the insulation collar is removed.
A second variant of the last-mentioned type of embodiment provides that the conductive trench filling is first sunk into the trench as far as a first sinking depth, the substrate is then uncovered at the sidewall of the trench and a dielectric layer is subsequently deposited directly onto the uncovered sidewall of the trench, and in that the conductive trench filling is subsequently sunk into the trench as far as a second sinking depth and the dielectric layer is removed from the sidewall of the trench before the epitaxial layer is grown. In this case the insulation collar is not covered by the dielectric layer, rather the latter is applied directly to the sidewall of the trench only after the insulation collar has been partially removed. In this variant of the above type of embodiment, the dielectric layer has the function of protecting the substrate at the trench sidewall during the second etching-back of the trench filling.
In the above types of embodiment, the sidewall of the trench is uncovered in each case in the upper region of the trench only as far as the first sinking depth and the conductive trench filling is spaced apart from the uncovered sidewall of the trench by a distance which approximately corresponds to the difference between the first and second sinking depths. The uncovering of the sidewall results in that the monocrystalline silicon of the substrate in which the trench is formed is uncovered. The epitaxially grown layer can subsequently be grown on the uncovered monocrystalline silicon of the substrate. Later, in a customary manner, a trench isolation is formed in the substrate and in the trench. The trench isolation isolates the present memory cell from adjacent memory cells, thereby preventing leakage currents.
It is preferably provided that the epitaxially grown layer is grown in such a way that a facet is formed with an angle of approximately 45 degrees relative to the substrate surface. The facet of the epitaxially grown layer has the advantage that the electrical connection of the conductive trench filling to the doping region of the selection transistor can be formed with a lower resistance on account of the geometrical configuration.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a semiconductor memory cell and a method for fabricating the memory cell, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.